LiquidSoC™

LiquidSoC is a revolutionary, patented methodology for creating custom SoCs using our LiquidIP solutions aimed at lowering costs, reducing risk and time to market. The heart of our innovative LiquidSoC technology is a high level holistic approach to IC design. Instead of designing ICs from a grouping of independent IP solutions, Rapid Bridge has developed a system of interdependent IP solutions combining industry leading performance with the lowest IC implementation risks. Integrating proven uniformed liquid building blocks together with an automated Base-SoC generator (SoComposer™), yields a system where end applications (Customer Specific Designs) can be implemented with only metal layers (CopperProfiler™). This creates a custom System on Chip (SoC) solution which fully leverages RapidBridge technology with customers own IP all within the industry standard EDA tool flows.

LiquidSoC

LiquidIP™

Our break thorough Liquid metal programmable Intellectual Property (IP) allows designers to rapidly create and configure a base platform which can be used with standard EDA flows.

LiquidIO™

LiquidIO supports over 40 industry standard interfaces with one common base IO cell. Each IO base cell is configured to one of the more than 40+ interface standards with a copper overlay cell, creating a truly flexible interface. LiquidIO and LiquidMXS solutions are controlled by a Central Calibration Unit that regulates voltage, current and impedances to improve signal quality and to reduce power/ground resources for ESD, Latchup and SSO

LiquidMXS™

LiquidMXS is a rich collection of metal programmable Mixed Signal (MXS) IP Blocks required to implement high level SoC subsystems and clocking networks. All LiquidMXS solutions utilize a single 218u x 270u MXS base cell preconfigured up to the contact layer. Surprisingly, all 15 flavors of PLLs, 4 types of DLLs, voltage regulation and decoupling capacitor are realized with the single MXS base cell

LiquidPHY™

LiquidPHY is a flexible subsystem that Rapid Bridge has developed to meet the challenging environment of nanometer designs. Just as a highly integrated SerDes utilizes a system level approach to achieve optimum performance/area/power characteristics, LiquidPHY applies such a system level approach to the integrated PHY and IO solutions

LiquidCell™

LiquidCell is the industry's first standard cell library solution to bring the rigorous DFM and Yield requirements of 32nm to current production nanometer nodes. Rapid Bridge LiquidCell library reduces the effects of On Chip Variation (OCV), process variation and defect density which translates directly to lower silicon costs. LiquidCell is comprised of an 700+ element metal programmable standard cell library supporting single and mixed Vt solutions.

LiquidMemory™

LiquidMemory is a multi port Register File compiler targeted for memory instances up to 8K bits. As with our LiquidCell offering, LiquidMemory Register Files are copper overlays that can be placed anywhere within the Sea of Transistor array.

LiquidSerDes™

LiquidSerDes is a comprehensive Serial Link solution that is register programmable to address multiple standards and configurations. Each four lane instance can support up to 4 interdependent SerDes lanes. LiquidSerDes is composed of a Physical Layer (PHY) - SerDes, CDR, PLL, Physical Coding Sub-layer (PCS) and all the associated test features.

SoComposer™

SoComposer is an EDA tool that allows ultra fast construction of LiquidSoC platforms (in less than a day). SoComposer accepts RapidBridge LiquidIP in addition to 3rd party and customer IPs to complement the LiquidSoC platform.

CopperProfiler™

CopperProfiler is an EDA tool that maps design specific IO, MXS and SRAM functions into an existing LiquidSoC platform. CopperProfiler outputs an industry standard database file used by standard floor planning and P&R EDA tools.

Features

  • Creation of LiquidSoC Platforms in less than 1-day
  • 90nm-45nm Platform Solutions
  • Uses Industry Standard EDA Tool Flows
  • Power/Performance/Area Efficiencies of SoC
  • Metal Configurable IO, PHY, MXS, SRAM, Standard Cell
  • 750 MHz system level performance (40 levels of logic)
  • Extraordinary ESD performance across all Interface Standards Passing 4kV HBM, 500V CDM

Benefits

  • Regular Structure of Layout Improves Yield: Lower Unit Costs
  • Seamless Integration of Customer and 3rd party IP
  • Automated Custom Platform Generation
  • Accelerated Time-Revenue
  • Lower Silicon integration Risks
  • Lower NRE & IP cost
  • Significant power reduction
  • Cost effective Derivative Product / Reusable Platform

Product Briefs

Feature Type Product Brief Data Sheet
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