LiquidSerDes™

LiquidSerDes is a comprehensive Serial Link solution that is register programmable to address multiple standards and configurations. Each four lane instance can support up to 4 interdependent SerDes lanes. LiquidSerDes is composed of a Physical Layer (PHY) - SerDes, CDR, PLL, Physical Coding Sub-layer (PCS) and all the associated test features.

The PCS block is configurable to meet multiple Serial Link applications. The smallest LiquidSerDes block can be configured to support up to 4-lanes. Additional lanes are realized with multiple instantiations to construct larger SerDes groupings such as 8 lane or 16 lane PCIexpress or Interlaken. Lower lane configurations may be realized by powering down extra lanes in a 4 lane family.

LiquidSerDes PHY layer incorporates a Scan Control Register (SCR) that is used to program the electrical characteristics of the PHY to comply with different standards. Hardened companion MAC and Control logic blocks are available to provide seamless interoperability.

Rapid Bridge, in conjunction with our 3rd party PCS/MAC IP partners, perform interoperability between the PHY and PCS/MAC IP blocks to allow for seamless implementation. Additionally, the PCS layer within the PHY can be tailored to different standards and applications (PCIe, Serial RapidIO, SATA, etc) for maximum flexibility.

Serial Link Features

Each lane contains a complete receive and transmit path, which incorporates a serializer and output driver on the transmit path and an input receiver and the de-serializer on the receive path. BIST circuitry for at-speed validation of the RX and TX paths and the respective multiplexers to allow for serial, parallel and line loop-backs are also incorporated in each lane.