LiquidPHY™

LiquidPHY is a flexible subsystem that Rapid Bridge has developed to meet the challenging environment of nanometer designs. Just as a highly integrated SerDes utilizes a system level approach to achieve optimum performance/area/power characteristics, LiquidPHY applies such a system level approach to the integrated PHY and IO solutions.

Unlike current PHY solutions, LiquidPHY contains IO, PHY functions and test circuitry all tightly integrated and residing within IO slots, creating the World's smallest and Fastest IO and PHY combination. One to one comparisons between LiquidPHY solutions and alternative solutions from IP vendors or IDMs clearly demonstrate LiquidPHY’s superior area, performance and power characteristics.

Combining LiquidPHY subsystems with LiquidIO offering (40+ interface standards), designers can take advantage of Rapid Bridge's high level integration, which results in the smallest possible IO ring, highest ESD protection and lowest power. In addition, integration of the PHY frees up substantial area in the SoC core. LiquidPHY+LiquidIO has consistently demonstrated die-area reduction of most pad limited designs by as much as 30%.

LiquidPHY also shares the revolutionary Rapid Bridge technology that makes these subsystem metal configurable. This additional feature enables designers to transform their sub-systems rapidly in a cost effective way by only changing a limited number of metal layers. This feature enables rapid yet simple customization of complex SoCs.

IO & PHY Portability

LiquidPHY offers complete PHY (DDR 2/3, RLDRAM2, GDDR, USB2.0, XGMII, SGMII, etc) solutions fully contained and embedded entirely within the IO ring for effortless lower risk implementation. Embedding the PHY eliminates the need to fix the physical placement of IO & PHY until late stages in the design implementation phase. With LiquidPHY, LiquidIO, LiquidMemory and LiquidCell solutions, full product customization is achieved by creating a new copper overlay profile.